A continuing goal of integrated circuit fabrication is to decrease the dimensions thereof. Integrated circuit dimensions can be decreased by reducing the dimensions and spacing of the constituent features or structures thereof. For example, by decreasing the dimensions and spacing of features (e.g., storage capacitors, access transistors, access lines, etc.) of a memory device, the overall dimensions of the memory device may be decreased while maintaining or increasing the storage capacity of the memory device.
Reducing the dimensions and spacing of semiconductor device features places ever increasing demands on the methods used to form the features. For example, due to limitations imposed by optics and radiation wavelengths, many conventional photolithographic methods cannot facilitate the formation of features having critical dimensions (e.g., widths, diameters, etc.) of less than about sixty (60) nanometers (nm). Electron beam (E-beam) lithography and extreme ultraviolet (EUV) lithography have been used to form features having critical dimensions less than 60 nm, but generally require complex processes and significant costs.
One approach for achieving features having critical dimensions of less than about 60 nm has been the use of pitch density multiplication processes, such as pitch density doubling processes. In a conventional pitch density doubling process, a photolithographic process is used to form photoresist lines over a sacrificial material over a substrate. The sacrificial material is etched using the photoresist lines to form mandrels, the photoresist lines are removed, spacers are formed on sides of the mandrels, and the mandrels are removed. The remaining spacers are used as a mask to pattern the substrate. Where the initial photolithography process formed one feature and one trench across a particular width of the substrate, after pitch density doubling, the same width of the substrate can include two smaller features and two smaller trenches, the width of each of the smaller trenches defined by the width of the spacers. Thus, the use of pitch density doubling can halve the minimum critical dimensions of features formed by the photolithographic processes, resulting in features having minimum critical dimension of about 30 nm. However, to achieve features having critical dimensions less than about 30 nm, the pitch density doubling process needs to be repeated (i.e., the process becomes a pitch density quadrupling process), significantly increasing processing time as well as energy and material costs.
Another approach for achieving semiconductor device features having critical dimensions of less than about 60 nm has been the use of self-assembling (SA) block copolymers. For example, an SA block copolymer deposited within a trench having particular graphoepitaxial characteristics (e.g., dimensions, wetting properties, etc.) may be annealed to form select morphology (e.g., spherical, lamellar, cylindrical, etc.) domains of one polymer block of the SA block copolymer within a matrix domain of another polymer block of the SA block copolymer. The select morphology domains or the matrix domain can be selectively removed, and the remaining select morphology domains or matrix domain utilized as an etch mask for patterning features into an underlying substrate. As the dimensions of the select morphology domains and the matrix domain are at least partially determined by the chain length of the SA block copolymer, feature dimensions much smaller than 60 nm are achievable (e.g., dimensions similar to those achievable through E-beam and EUV lithography processes). Such methods have, for example, been used to form close-packed, hexagonal arrays of openings in an underlying substrate. However, certain semiconductor device structures may utilize different (i.e., non-hexagonal) array configurations. For example, Dynamic Random Access Memory (DRAM) device structures may utilize rectilinear arrays of openings (e.g., contact openings) rather than hexagonal arrays of openings.
A need, therefore, exists for new, simple, and cost-efficient methods of forming a rectilinear array of openings for a semiconductor device structure, such as, for example, a rectilinear contact array for a memory device structure, that enables the formation of the closely packed openings having critical dimensions (e.g., widths, diameters, etc.) less than or equal to about 30 nm.